1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the contact level of a semiconductor device, in which contact areas, such as drain and source regions, as well as gate electrode structures, are connected to the metallization system of the semiconductor device.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very high number of circuit elements, especially transistors, are provided and operated on a restricted chip area. Although immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of the circuit elements, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed thereof. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits including logic portions fabricated by MOS technology, field effect transistors (FETs) are provided that are typically operated in a switched mode, that is, these devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
On the basis of the field effect transistors, more complex circuit components may be composed, such as inverters and the like, thereby forming complex logic circuitry, embedded memories and the like. Due to the reduced dimensions, the operating speed of the circuit components has been increased with every new device generation, wherein, however, the limiting factor of the finally achieved operating speed of complex integrated circuits is no longer the individual transistor element but the electrical performance of the complex wiring system, which may be formed above the device level including the actual semiconductor-based circuit elements, such as transistors and the like. Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the inner-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, which connects, with one end, to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and, with another end, to a respective metal line in the metallization layer and/or to a contact region of a further semiconductor-based circuit element, in which case the interconnect structure in the contact level is also referred to as a local interconnect. The contact structure may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. Upon further shrinkage of the critical dimensions of the circuit elements in the device level, the dimensions of metal lines, vias and contact elements also have to be adapted to the reduced dimensions, thereby requiring sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels, metal lines and vias having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required “packing density” in accordance with density of circuit elements in the device level.
Upon further reducing the dimensions of the circuit elements, for instance using critical dimensions of 50 nm and less, the contact elements in the contact level have to be provided with critical dimensions on the same order of magnitude. The contact elements typically represent plugs, which are formed of an appropriate metal or metal composition, wherein, in sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically the interlayer dielectric material is formed first and is patterned so as to receive contact openings, which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements. In particular, in densely packed device regions, the lateral size of the drain and source areas and thus the available area for the contact regions is 100 nm and significantly less, thereby requiring extremely complex lithography and etch techniques in order to form the contact openings with well-defined lateral dimensions and with a high degree of alignment accuracy.
With reference to FIG. 1, the critical situation upon forming contact elements in densely packed device areas will be described in more detail. FIG. 1 schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101, such as a silicon substrate and the like, in or above which is provided a silicon-based semiconductor layer 102. In the example shown, the substrate 101 and the layer 102 form a bulk configuration, i.e., the layer 102 initially represents a portion of a crystalline material of the substrate 101. In other cases, a buried insulating material may be formed below the semiconductor layer 102, thereby providing a silicon-on-insulator (SOI) architecture.
Furthermore, in the advanced manufacturing stage shown in FIG. 1, the semiconductor layer 102 is typically divided into a plurality of active regions or semiconductor regions by means of appropriate isolation structures, wherein, for convenience, a single active region 102A and a corresponding isolation region 102C are illustrated so that the active region 102A is laterally delineated by the isolation region 102C. Generally, an active region is to be understood as a semiconductor region in and above which one or more transistors are to be formed. In the present example, the active region 102A is to be understood as a densely packed device region since here a plurality of transistors 150 are formed in and above the active region 102A, thereby requiring a minimum lateral distance or pitch between the corresponding gate electrode structures 160A, 160B, 160C, 160D of the transistors 150. For example, a length of the gate electrode structures 160A, 160B, 160C, 160D may be 40 nm and less, wherein generally the length direction of the transistors 150 and of the active region 102A is represented by the horizontal direction in FIG. 1. Similarly, a width direction is to be understood as a direction extending perpendicularly to the drawing plane of FIG. 1.
In sophisticated semiconductor devices, generally performance of transistors may be enhanced by a plurality of techniques, in addition to continuously reducing the gate length and thus the channel length of the field effect transistors. For example, in some strategies, the charge carrier mobility in channel regions 153, i.e., in regions positioned below the gate electrode structures 160A, 160B, 160C, 160D and laterally confined by respective drain and source regions 151, may be increased by inducing certain stress conditions therein, thereby also enhancing drive current capability and thus switching speed. In this manner, in particular performance of transistors in logic circuit portions may be enhanced since here a high drive current capability in combination with high switching speed at moderately low threshold voltage values is typically required. To this end, a plurality of strain-inducing mechanisms have been developed, which may be implemented in the transistors 150, which, however, are not shown in FIG. 1. Moreover, generally, a reduction of length of the channel regions 153 is associated with an increase of the capacitive coupling between the gate electrode and the channel region, in particular in high performance transistors, and, for this reason, typically the gate dielectric material separating the channel region 153 from an electrode material of the gate electrode structures is reduced in thickness. In the past, silicon dioxide-based gate dielectric materials have been used due to the superior characteristics of a silicon/silicon dioxide interface with respect to high temperature treatments and the like, wherein, however, upon continuously shrinking the critical dimensions of the transistors, the moderately low dielectric constant of silicon dioxide-based dielectric materials may require a thickness of 2 nm and less of a corresponding gate insulation layer in order to comply with the performance requirements of transistors having a gate length well below 80 nm. In this case, however, the resulting leakage currents caused by hard carrier injection direct tunneling of charge carriers through the extremely thin silicon dioxide-based gate dielectric may no longer be compatible with thermal design power requirements. Therefore, new strategies have been developed in which at least a significant portion of the conventional gate dielectric material is replaced by a dielectric material of increased dielectric constant, wherein any such materials are typically referred to as high-k dielectric materials and have a dielectric constant of 10.0 and higher. For example, a plurality of metal oxides and silicates, such as hafnium oxide, zirconium oxide and the like, may be efficiently used as high-k dielectric materials. It turns out, however, that the incorporation of the high-k dielectric material also requires appropriately adapted strategies for adjusting the work function values of the gate electrode structures, which in turn requires the incorporation of specific work function metal species, such as titanium, tantalum, aluminum, lanthanum and the like, which may also be used as efficient electrode metals, thereby also increasing electrical conductivity and reducing degradation of any depletion zones in the vicinity of the gate dielectric material, as is also typically encountered in conventional silicon dioxide/polysilicon gate electrode structures. Since the high-k dielectric materials and the work function metal species may be highly sensitive with respect to high temperature treatments and the exposure to critical process atmospheres, as are typically encountered during the entire manufacturing process, in some very promising approaches, these materials are provided in a very late manufacturing stage on the basis of a so-called replacement gate approach.
Therefore, the gate electrode structures 160A, 160B, 160C, 160D are provided in the form of replacement gate structures comprising a gate dielectric material 165, which in turn includes a high-k dielectric material, and an electrode material 167, which may also include an appropriately selected work function metal species.
The semiconductor device 100 further comprises a contact level 120, which comprises a plurality of dielectric materials, such as a dielectric etch stop layer 121, typically provided in the form of a silicon nitride material, followed by a dielectric layer 122, such as a silicon dioxide-based material, or any other appropriate dielectric material which substantially fills the space between the densely packed gate electrode structures 160A, 160B, 160C, 160D. Furthermore, a further dielectric material 123 or material system may be provided in the form of silicon dioxide, possibly in combination with a silicon nitride material (not shown) and the like. Furthermore, as discussed above, contact elements 125 are formed so as to connect to the active region 102A, i.e., to appropriate contact regions within the drain and source areas 151, which are provided in the form of metal silicide regions 152, which may be comprised of any appropriate metal species, such as nickel, platinum and the like. The contact elements 125 typically comprise a contact metal, such as tungsten, indicated by 124A, typically in combination with appropriate barrier materials, such as titanium, titanium nitride and the like, which are for convenience not illustrated in FIG. 1. As shown, one of the contact elements 125, indicated by (a), is misaligned with respect to the gate electrode structure 160A and thus results in a short-circuit between the electrode material 167 and the conductive material 124A. In this case, a severe device failure may occur. Moreover, for the remaining contact elements, a degree of misalignment may be less pronounced so as to avoid a short-circuit between the associated gate electrode structures, wherein, however, nevertheless varying transistor characteristics may be obtained that depend on the alignment accuracy when forming the contact elements 125. For example, the size of the corresponding metal silicide region 152T for the contact element 125 (b) depends on the positioning of the contact element and thus the corresponding overall series resistance of the transistor as well as the parasitic capacitance significantly depends on the alignment accuracy and thus on the patterning strategy used for forming the contact elements 125.
The semiconductor device 100 as shown in FIG. 1 may be formed on the basis of the following process strategy. The active region 102A in combination with the isolation region 102C is formed by using well-established lithography, etch, deposition, anneal and material removal processes in combination with implantation sequences and associated masking regimes. Thereafter, according to replacement gate approaches, a substantially conventional gate layer stack, for instance based on silicon dioxide and polysilicon material, is provided in combination with additional hard mask materials, such as silicon nitride and the like, and the resulting layer stack is then patterned on the basis of sophisticated lithography and etch techniques, for instance on the basis of double exposure, double etch strategies for patterning the corresponding hard mask material in order to provide the resulting gate electrode structures with the desired lateral dimensions. Typically, the resulting gate electrode structures comprise a dielectric cap material, which may represent the residue of a hard mask material, for instance provided in the form of silicon nitride, silicon dioxide and the like. Thereafter, the further processing is continued by forming the drain and source regions 151 in combination with a spacer structure 164, which is typically accomplished by well-established deposition and etch techniques, while the drain and source regions 151 may be formed by selective epitaxial growth techniques, implantation processes, or any combination thereof. After any high temperature processes, the materials 121 and 122 are deposited by plasma enhanced chemical vapor deposition (CVD) and the like, followed by planarization and removal of any excess material, which is typically accomplished by applying at least one chemical mechanical polishing (CMP) process. During the corresponding planarization process, also a surface of a polysilicon material is exposed and the polysilicon material is then selectively removed on the basis of highly selective wet chemical etch recipes, plasma assisted etch recipes and the like. Next, a complex deposition and patterning regime is applied in order to incorporate the gate dielectric material 165 that includes the high-k dielectric material followed by the deposition of appropriately selected work function metal species and an electrode metal, which may be provided in the form of aluminum, aluminum alloys and the like. It should be appreciated that respective work function metal species may have to be provided differently for N-channel transistors and P-channel transistors, or differently for transistors requiring different threshold voltage values and the like. After removing any excess material and performing a heat treatment for thermally stabilizing and diffusing the work function metal species, the processing is continued, for instance, in some approaches, by taking advantage of the substantially planar surface conditions and forming a first portion of the contact elements 125 by applying highly sophisticated and critical lithography and etch techniques in order to etch into the materials 122 and 121 laterally adjacent to the gate electrode structures 160A, 160B, 160C, 160D so as to connect to the drain and source regions 151. To this end, a plurality of appropriately shaped contact openings are typically formed, thereby requiring extremely sophisticated lithography techniques, which have to ensure a high alignment accuracy, which, however, due to the reduced pitch, may nevertheless result in a certain degree of misalignment as, for instance, shown for the contact elements 125. Thereafter, a dielectric material 123 is formed and appropriately patterned so as to form contact openings connecting to the previously formed contact elements and also connecting to the gate electrode structures 160A, 160B, 160C, 160D as required by the overall circuit layout, wherein any such contacts are typically provided outside of the active region 102A in order to avoid gate contact failures, i.e., short circuits with the drain and source regions with a certain degree of misalignment. In other strategies, the contact elements 125 may be formed in a single patterning process, i.e., after providing the material 123, thereby also requiring extremely sophisticated lithography techniques and etch recipes, since in this case the patterning process has to be performed for contact openings of very different depth, i.e., for contact openings connecting to the gate electrode structures and contact openings connecting to the drain and source regions 151.
In the former approach for forming the contact elements 125 prior to actually depositing the contact material 124A, for instance in the form of tungsten, typically the metal silicide regions 152 are provided on the basis of well-established silicidation regimes in order to further reduce the overall contact resistivity, wherein the resulting transistor characteristics may thus significantly depend on the alignment accuracy, as is also discussed above.
Hence, in order to provide superior uniformity of the resulting transistor characteristics and reduced yield loss caused by short circuits between the contact elements and the gate electrode structures, a “self-aligned” patterning regime would be desirable in which the contact openings and thus the contact elements, at least within the dielectric material 122, could be provided, for instance, on the basis of etch strategies which are highly selective with respect to the gate electrode structures. In this case, the gate electrode structures have to be reliably encapsulated by any appropriate etch stop material which, however, is not compatible with sophisticated replacement gate approaches, as described above, since here the top surface of the electrode material is exposed and would require a dedicated etch stop material, which in turn would have to be provided on the basis of an extremely complex lithography and patterning process, thereby resulting in even more process non-uniformities.
In view of the situation described above, the present disclosure relates to process techniques and semiconductor devices in which sophisticated high-k metal gate electrode structures may be provided on the basis of a replacement gate approach, as may be required for high performance transistors, while, on the other hand, contact elements may be provided, while avoiding or at least reducing the effects of one or more of the problems identified above.